1 of 10 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? directly replaces 8k x 8 volatile static ram or eeprom ? unlimited write cycles ? low - power cmos ? jedec standard 28 - pin d ip package ? read and write access times of 70 ns ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? full 10% v cc operating range (ds1225ad) ? optional 5% v cc operating range (ds1225ab) ? optional industrial temperature range of - 40c to +85c, designated ind pin assignment 28- pin encapsulated package 720- mil extended pin description a0 -a12 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+5v) gnd - ground nc - no connect description the ds1225ab and ds1225ad are 65,536 - bit, fully static, nonvolatile srams organized as 8192 wor ds by 8 bits. each nv sram has a self - contained lithium energy source and control circuitry which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write prot ection is unconditionally enabled to prevent data corruption. the nv srams can be used in place of existing 8k x 8 sr ams directly conforming to the popular bytewide 28 - pin dip standard. the devices also match the pinout of the 2764 eprom an d the 2864 eepro m, allowing direct substitution while enhancing performance. t here is no limit on the number of write cycles that can be executed and no additional support cir cuitry is required for microprocessor interfacing. ds1225ab/ad 64k nonvolatile sram www.maxim - ic.com 15 13 27 a7 a5 a3 a2 a1 a0 dq0 dq1 gnd dq2 vcc we nc a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq3 dq4 1 2 3 4 5 6 7 8 9 10 11 12 14 28 26 25 24 23 22 21 20 19 18 17 16 a12 a6 a4 nc 19 - 5625 ; rev 11/1 0 downloaded from: http:///
ds1225ab/ad 2 of 9 read mode the ds1225ab and ds1225ad execute a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 13 address inputs (a 0 -a 12 ) defines whi ch of the 8192 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe access times are also satisfied. if ce and oe access times are not satisfied, then data access must be measured from the later - occurring signal and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1225ab and ds1225ad execute a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the later - occurri ng falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier risin g edge of ce or we . all address inputs must be ke pt valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the ou tput drivers are enabled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1225ab provi des full functional capability for v cc greater than 4.75 volts and write protects by 4.5 volts. the ds1225ad provides full - functional capability for v cc greater than 4.5 volts and write protects by 4.25 volts. data is maintained in the absence of v cc witho ut any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become dont care, and all outputs become high - impedance. as v cc fa lls below approximately 3.0 volts, the power switching circuit connec ts the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.75 volts for the ds1225ab and 4.5 volts for the ds1225ad. freshness seal each ds1225 is shipped from maxim with the lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level of greater than v tp , the lithium energy source is enabled for battery backup operation. downloaded from: http:///
ds1225ab/ad 3 of 9 absolute maximum ratings voltage on any pin relative to ground - 0.3v to +6.0v operating temperature commercial: 0c to +70c industrial: - 40c to +85c storage temperature - 40c to +85c lead temperature (soldering, 10 s) +260c note: edip is wave or hand soldered only. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maxi mum rating conditions for extended periods of time ma y affect reliability. reco mmended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes ds1225ab power supply voltage v cc 4.75 5.0 5.25 v ds1225ad power supply voltage v cc 4.50 5.0 5.5 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 +0.8 v (t a : see note 10) (v cc =5v 5% for ds1225ab) dc electrical characteristics (v cc =5v 10% for ds1225ad) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce > v ih < v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce =2.2v i ccs1 5.0 10.0 ma standby current ce =v cc - 0.5v i ccs2 3.0 5 .0 ma operating current (commercial) i cc01 75 ma operating current (industrial) i cc01 85 ma write protection voltage (ds1225ab) v tp 4.50 4.62 4.75 v write protection voltage (ds1225ad) v tp 4.25 4.37 4.5 v capacitance (t a = + 25c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf downloaded from: http:///
ds1225ab/ad 4 of 9 (t a : see note 10) (v cc =5v 5% for ds1225ab) ac electrical characteristics (v cc =5v 10% for ds1225ad) parame ter symbol ds1225ab-70 ds1225ad-70 units notes min max read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 35 ns ce to output valid t co 70 ns oe or ce to output active t coe 5 ns 5 output high z from deselection t od 25 ns 5 output hold from address change t oh 5 ns write cycle time t wc 70 ns write pulse width t wp 55 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 0 10 ns ns 12 13 output high z from we t odw 25 ns 5 output active from we t oew 5 ns 5 data setup time t ds 30 ns 4 data hold time t dh1 t dh2 0 10 ns ns 12 13 downloaded from: http:///
ds1225ab/ad 5 of 9 read cycle see note 1 write cycle 1 see notes 2, 3, 4, 6, 7, 8 and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8 and 13 downloaded from: http:///
ds1225ab/ad 6 of 9 power - down/power - up condition see note 11 power - down/power - up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 300 s v cc slew from 0v to v tp t r 300 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms (t a = + 25c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative und ershoots, of any amplitude, allowed when device is in battery backup mode. downloaded from: http:///
ds1225ab/ad 7 of 9 notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high - impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition oc curs simultaneously with or later than the we low transition, the output buffers remain in a high - impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high - impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low t ransition, the output buffers remain in a high - impedance state during this period. 9. each ds1225ab and each ds1225ad has a built - in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. this pa rameter is guaranteed by design and is not 100% tested. 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commer cial products, this range is 0c to 70c. for industrial products (ind ), this range is - 40c to +85c. 11. in a power down condition the voltage on any pin may not exceed the voltage o n v cc . 12. t wr1 , t dh1 are measured from we going high. 13. t wr2 , t dh2 are measured from ce going high. 14. ds1225 modules are recognized by underwriters laborator ies (u l ) under file e99151. dc test conditions outputs open cycle = 200ns for operating current all voltages are referenced to ground ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0 - 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns downloaded from: http:///
ds1225ab/ad 8 of 9 ordering information part temp range supply tole rance pin - package speed grade (ns) ds1225ab-70+ 0c to +70c 5v 5% 28 720 edip 70 ds1225ab- 70ind+ - 40c to +85c 5v 5% 28 720 ed ip 70 ds1225ad-70+ 0c to +70c 5v 10% 28 720 edip 70 ds1225ad-70i nd+ - 40c to +85c 5v 10% 28 720 edip 70 + denotes a lead (pb) - free/rohs - compliant p ackage. package information for the latest package outline information and land pat terns, go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs sta tus. package type package code outline no. land pattern no. 28 edip mdt28+2 21-0245 downloaded from: http:///
ds1225ab/ad 9 of 9 revision history revision date description pages changed 121907 added package information table ; r emoved the dip module package drawing and dimension table 9 11/10 updated the storage information, soldering temperature, and lead temperature information in the absolute maximum ratings section; removed the -85, - 150, and -200 min/max information from the ac electrical characteristics table; updated the ordering information table (removed -85, -150 , and -200 parts and leaded -70 parts) 1, 3, 4 , 8 downloaded from: http:///
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